High speed multiplier using high accuracy oating point logarithmic number system
نویسنده
چکیده
a. Department of Electronics and Communication Engineering, National Institute of Technology, Meghalaya, Shillong, Meghalaya-793003, India. b. Department of Electronics and Communication Engineering, JIS College of Engineering, Kalyani, West Bengal-741235, India. c. Department of Electronics and Telecommunication Engineering, Bengal Engineering and Science University, Shibpur, Howrah-711103, India.
منابع مشابه
A floating point multiplier performing IEEE rounding and addition in parallel
This work was one of ASIC basis technology project mainly managed by IDEC and supported by the ministry of trade, industry & energy and the ministry of science and technology of korea. Abstract In the conventional oating point multipliers, the rounding stage is usually constructed by using a high speed adder for the increment operation, increasing the overall execution time and occupying a larg...
متن کاملA Proficient Low Power Logarithmic Multiplier Using Iterative Pipeline Technique
Multiplication is the basic function performed in digital signal processors (DSP) and multimedia processors. Applications in DSP heavily rely on multiplication with high performance as a prime target but the major requirement is complex data handling. So, logarithmic multiplier is a practical solution for DSP functions that performs multiplication using simple addition operation. The LNS system...
متن کاملDesign and Implementation of a High Speed Systolic Serial Multiplier and Squarer for Long Unsigned Integer Using VHDL
A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of func...
متن کاملDesign and Implementation of a High Speed Systolic Serial Multiplier and Squarer for Long Unsigned Integer Using VHDL
A systolic serial multiplier for unsigned numbers is presented which operates without zero words inserted between successive data words, outputs the full product and has only one clock cycle latency. 
The multiplier is based on a modified serial/parallel scheme with two adjacent multiplier cells. Systolic concept is a well-known means of intensive computational task through replication of fu...
متن کاملDesign of a Multiplier for Similar Base Numbers Without Converting Base Using a Data Oriented Memory
One the challenging in hardware performance is to designing a high speed calculating unit. The higher of calculations speeds in a computer system will be pointed out in terms of performance. As a result, designing a high speed calculating unit is of utmost importance. In this paper, we start design whit this knowledge that one multiplier made of several adder and one divider made of several su...
متن کامل